1. Field of the Invention
The present invention relates to a packet-type memory Large Scale Integration circuit (LSI) having a packet-type memory bus and interface to be preferably used for a large-capacity memory LSI, particularly to a memory system of a processing-function-provided packet-type memory LSI configured for adding a processing function to a packet-type memory LSI and a method for controlling the memory system.
2. Description of the Prior Art
Japanese Patent Laid-Open No. 10-049428 specification (Japanese Patent Application No. 08-204668) discloses an art for constituting a processing-function-provided memory system by using a memory LSI and a processing-function-provided memory LSI.
Moreover, relating to the above art, Japanese Patent Application No. 09-097587 which was applied prior to this application but which was not released when this application was applied discloses an art for configuring a similar processing-function-provided memory system by particularly using a packet-type memory LSI and a processing-function-provided packet-type memory LSI.
In this case, a packet-type memory LSI represents a memory LSI for performing memory access by using a packet such as a Direct Rambus DRAM (Direct Rambus Dynamic Random Access Memory) (referred to as DRDRAM) or a Synchronous-Link DRAM (Synchronous-Link Dynamic Random Access Memory) (referred to as SLDRAM) and it is described in detail in xe2x80x9cDirect Rambus Technology: The New Main Memory Standardxe2x80x9d on pp. 18-28 and xe2x80x9cSLDRAM: High-Performance, Open-Standard Memoryxe2x80x9d on pp. 29-39 in November/December 1997 issue of Journal for xe2x80x9cIEEE Micro.xe2x80x9d
Moreover, a coprocessor-contained packet-type memory LSI represents a packet-type memory LSI configured by containing a coprocessor in an LSI. As for this specification, LSIs including those having a processing function other than a coprocessor are referred to as xe2x80x9cprocessing-function-provided packet-type memory LSI.xe2x80x9d
In general, a memory system is configured by arranging a plurality of memory LSIs but it has only a function for storing the data used for processing. However, the processing-function-provided memory system disclosed in the official gazette of Japanese Patent Laid-Open No. 10-049428 specification is configured by using a memory LSI and a processing-function-provided memory LSI, which makes it possible to perform processing by a processing-function-provided memory LSI in the processing-function-provided memory system.
Moreover, the processing-function-provided packet-type memory system disclosed in the above Japanese Patent Application No. 09-097587 is configured by using a packet-type memory LSI and a processing-function-provided packet-type memory LSI, which controls execution of processing by the processing-function-provided packet-type memory LSI by using a packet instead of using the above mechanism of making memory access to a packet-type memory LSI by using a packet.
Moreover, Japanese Patent Laid-Open No. 61-91757 specification discloses a data transfer controller. The data transfer controller is configured of two controllers connected to each other by a bi-directional data bus, a plurality of control lines and an input/output unit connected to the bi-directional data bus which transfers data to and from only one of the two controllers. During data transfer for each unit-length data is performed through the bi-directional data bus while asynchronously confirming an other-controller""s response signal to one-controller""s request signal through the control line between the two controllers, one controller can transfer data to and from the input/output unit through the bi-directional data bus when the other controller switches transfer modes for the bi-directional data bus. Moreover, a monitoring signal line for inverting the logical state of a monitoring signal by responding start or end of data transfer between the two controllers is used as the control line and at least the other of the two controllers has decision means for deciding the validity of the logical state of the monitoring signal.
Furthermore, the official gazette of Japanese Patent Laid-Open No. 63-88666 specification discloses a bus adjustment controller. The bus adjustment controller is provided with a microprocessor not containing a bus-using-right adjustment function and a direct memory access controller for obtaining or resigning the bus-using right through the handshake system between a bus-using request signal and a bus-using permission signal to adjust the competition for bus-using produced between the microprocessor and the direct memory access controller.
Furthermore, Japanese Patent Laid-Open No. 63-106035 specification discloses a semiconductor file memory apparatus. The semiconductor file memory comprises an auxiliary memory using a semiconductor memory connected to a computer system to store and write/read or read data wherein the semiconductor file memory is a large-capacity semiconductor file memory configured from a Small Computer Systems Interface (SCSI) protocol control circuit, a microprocessor, a Direct Memory Access (DMA) control circuit, a bus drive, and a semiconductor memory provided with an address decoding circuit so that data can be transferred at a high speed when connected to the SCSI bus.
Furthermore, Japanese Patent Laid-Open No. 2-120961 specification discloses an invention related to an inter-memory data transfer system. The system comprises an information processor configured of at least a processor, a memory, and a DMA controller are connected by a local bus to a plurality of arithmetic units, are connected by a mutual connection line wherein the DMA controller in each arithmetic unit has at least a function for obtaining the bus-using right from the processor in the arithmetic unit, a function for resigning the bus-using right, a function for reading or writing data in a memory through the bus, a function for providing an instruction for the DMA controllers connected to other arithmetic units, a function for receiving instructions from the DMA controllers of the arithmetic units, a function for executing instructions supplied from DMA controllers of the arithmetic units, and a function for reading or writing data from or in memories of these arithmetic units and moreover, these functions can be separately and independently operated. Moreover, the DMA controller of a first arithmetic unit makes it possible to mutually perform data read and write operations between the memory of the first arithmetic unit and the memory of a second arithmetic unit via the mutual connection line with the processor of the first arithmetic unit and the processor of the second arithmetic unit separated from each bus.
Furthermore, Japanese Patent Laid-Open No. 8-235106 specification discloses an interfacing method and a system for an upgrade processor. This provides a method and a system for interfacing an upgrade processor and a data processing system having data bus widths different from each other. Specifically, the data processing system has a first processor having an m-byte data width, an n-byte data bus (mxe2x89xa7n), and a second processor connected to the bus to execute bus transaction by using an n-byte data packet. An adapter electrically connected between the first processor and the bus converts an n-byte data packet input from the bus into an m-byte data packet and an m-byte data packet input from the first processor into an n-byte data packet. Thereby, the first processor can transfer data to and from the bus by using the m-byte data packet. The second mode is a method and a system for adjusting the portion between two buses and masters having bus-obtaining protocols different from each other.
As for the memory system disclosed in the above prior application, a processing-function-provided memory system, particularly a processing-function-provided packet-type memory system is constituted by directly using a conventional memory bus, particularly, the conventional configuration of a packet-type memory bus. This is due to the following reason.
In general, as for a memory bus, because a bus master allowed to issue a command onto a bus is only a memory controller LSI, adjustment of the exclusive right of a memory bus is unnecessary. Moreover, because communication performed on a memory bus is only memory access such as read or write, the number of communication formats is small and the communication protocol is relatively simple.
Thus, because the protocol is simple, a processing-function-provided memory system using a conventional memory bus has a feature of capable of executing mutual communication through the memory bus in a short time.
Because a processing-function-provided memory system is a system including the function of a conventional system, how to decrease a delay time under memory access is a large problem together with improvement of a data band width.
Therefore, it can be said that the above feature is very suitable for the bus of a processing-function-provided memory system.
However, the fact that only a memory controller LSI can serve as a bus master means that a processing-function-provided memory LSI cannot serve as a bus master by performing the interrupt operation from the processing-function-provided memory LSI to a memory controller LSI.
Moreover, To make a processing-function-provided memory LSI perform complex processing, it is necessary to realize the above interrupt operation and make it possible for the processing-function-provided memory LSI to serve as a bus master.
Moreover, a bus-connection-type parallel processing system in which a plurality of processors is connected to one processor bus to perform parallel operation is present as a system using a plurality of bus masters. The communication protocol of the processor bus of the bus-connection-type parallel processing system is very complex compared to the communication protocol of a memory bus. This is due to several reasons.
The first reason is that a processor bus assumes that a plurality of bus masters is present. Therefore, these bus masters may simultaneously issue requests to the processor bus and thereby, it is necessary to control the exclusive right of the processor bus for determining which bus master can issue a request.
Moreover, to avoid dead lock or live lock, it is necessary to control a flow on a processor bus.
Furthermore, to improve the efficiency of parallel processing or distributed processing, it is necessary to support communication formats on many types of buses or communication patterns on many types of buses.
Furthermore, it may be necessary to incorporate a mechanism for assuring the consistency of the data between a plurality of processors such as cache coherency into protocols.
Thus, because communication protocols are complex, these systems have a problem that mutual communication through a processor bus requires a lot of time although a plurality of bus masters can be permitted.
Therefore, the present invention is made in accordance with the recognition of the above technical problems and its main object is to provide a more-flexible and higher-performance processing-function-provided memory system and the control means for the same, making it possible for a processing-function-provided packet-type memory LSI to serve as a bus master while basically using the processing-function-provided packet-type memory LSI and a processing-function-provided packet-type memory system.
It is another object of the present invention to realize a processing-function-provided packet-type memory LSI provided with an external input/output terminal constituted by adding several signal lines to a packet-type memory through the above new packet-type memory bus art and provide a processing-function-provided memory system and the control means of the same, making it possible to use the processing-function-provided packet-type memory LSI and a conventional packet-type memory LSI by connecting them to the same packet-type memory bus.
It is still another object of the present invention to provide a processing-function-provided memory system and control means of the same for realizing memory access to the packet-type memory LSI and processing-function-provided packet-type memory LSI connected to the above packet-type memory bus without temporal overhead due to addition of a processing function.
A processing-function-provided packet-type memory system of the present invention for attaining the above objects is a processing-function-provided packet-type memory system configured of a plurality of packet-type memory LSIs, one processing-function-provided packet-type memory LSI, and one memory controller LSI, in which the memory controller LSI, packet-type memory LSI, and processing-function-provided packet-type memory LSI are connected by bi-directional data bus and command bus and moreover, the memory controller LSI and the processing-function-provided packet-type memory LSI are connected by a unidirectional ready signal line extending toward the memory controller LSI and a bus adjustment signal line serving as a bi-directional signal line.
Moreover, it is possible to provide a processing-function-provided packet-type memory system of the present invention as a processing-function-provided packet-type memory system configured of a plurality of packet-type memory LSIs, one processing-function-provided packet-type memory LSI, and one memory controller LSI, with the memory controller LSI, packet-type memory LSI, and processing-function-provided packet-type memory LSI connected by bi-directional data bus and command bus wherein the memory controller LSI and processing-function-provided packet-type memory LSI are connected by a unidirectional ready signal line extending toward the memory controller LSI and a processing-function-provided packet-type memory interrupt signal line serving as a unidirectional signal line extending from the memory controller LSI.
A method of the present invention for controlling a processing-function-provided packet-type memory system requests transfer of the exclusive right of a command bus from a memory controller LSI to a processing-function-provided packet-type memory LSI or from the processing-function-provided packet-type memory LSI to the memory controller LSI through a bus adjustment signal line.
A method of the present invention for controlling a processing-function-provided packet-type memory system requests transfer of the exclusive right of a command bus from a memory controller LSI to a processing-function-provided packet-type memory LSI through a memory controller interrupt signal line and moreover requests transfer of the exclusive right of the command bus from the processing-function-provided packet-type memory LSI to the memory controller LSI through a processing-function-provided packet-type memory interrupt signal line.
A method of the present invention for controlling a processing-function-provided packet-type memory system transfers the exclusive right of a command bus to a processing-function-provided packet-type memory LSI by transmitting an exclusive-right transfer command packet from a memory controller LSI to the processing-function-provided packet-type memory LSI through the command bus when the memory controller LSI has the exclusive right of the command bus and the processing-function-provided packet-type memory LSI requests transfer of the exclusive right of the command bus.
Moreover, a method of the present invention for controlling a processing-function-provided packet-type memory system transfers the exclusive right of a command bus to a memory controller LSI by transmitting an exclusive transfer command packet from a processing-function-provided packet type memory LSI to the memory controller LSI through the command bus when a processing-function-provided packet-type memory LSI has the exclusive right of the command bus and the memory controller LSI requests transfer of the exclusive right of the command bus.
Furthermore, as for a processing-function-provided packet-type memory system of the present invention, a packet-type memory LSI has an intrinsic device ID, a processing-function-provided packet-type memory LSI has an intrinsic device ID, and a memory controller LSI has an intrinsic device ID.
Furthermore, a method of the present invention for controlling a processing-function-provided packet-type memory system designates a memory controller LSI by using a device ID intrinsic to the memory controller LSI and transmits a command packet to the memory controller LSI when a processing-function-provided packet-type memory LSI obtains the exclusive right of a command bus.
Furthermore, a method of the present invention for controlling a processing-function-provided packet-type memory system notify a memory controller LSI whether a processing-function-provided packet-type memory LSI completes processing or the processing-function-provided packet-type memory LSI is ready to transfer an exclusive right to a memory controller LSI from the processing-function-provided packet-type memory LSI through a ready signal line.